ESD/EOS protection circuits for integrated circuits

Details ESD/EOS protection circuits for integrated circuits ESD/EOS protection circuits for integrated circuits

1993-03-31

1995-09-12

Hoff, Marc S.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 91, 361118, H02H 324

Patent

active

054502675

ABSTRACT:
An ESD/EOS protection circuit 10. Trigger nMOS transistor M1 has a drain 20 connected to a voltage pad 22, a gate 24 connected to ground 26 and a source 28 connected to ground 26 through source resistor R.sub.e. Switch control nMOS transistor M2 has a drain 30, a gate 34 connected to source 28 of transistor M1, and a source 38 connected to ground 26. Current controlled switch (CCS) 40 is connected to voltage pad 22, ground 26 and drain 30 of transistor M2. CCS 40 is a bipolar pnp-based current controlled switch.

REFERENCES:
patent: 5077591 (1991-12-01), Chen et al.
patent: 5086365 (1992-02-01), Lien

Affiliated with

Also associated with

Rating

ESD/EOS protection circuits for integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with ESD/EOS protection circuits for integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and ESD/EOS protection circuits for integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-409882