ESD configuration for low parasitic capacitance I/O

Details ESD configuration for low parasitic capacitance I/O ESD configuration for low parasitic capacitance I/O

2011-04-05

2011-04-05

Fureman, Jared J (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S091100, C361S111000

Reexamination Certificate

active

07920366

ABSTRACT:
An integrated circuit can include an I/O pad, an internal circuit, an inductor, an electrostatic discharge (ESD) protection circuit, and an ESD clamp. The internal circuit can be biased with a first voltage supply and a second voltage supply, where the internal circuit is connected to the I/O pad at a first node. The ESD protection circuit can be connected between the first node and a second node. The inductor can be connected between the second node and a third voltage supply. Further, the ESD clamp can be connected between the second node and the second voltage supply.

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