ESD clamp with “trailing pulse” suppression

Details ESD clamp with “trailing pulse” suppression ESD clamp with “trailing pulse” suppression

2007-09-25

2007-09-25

Leja, Ronald W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

11131105

ABSTRACT:
In a method and system for protecting a semiconductor device from an electrostatic discharge (ESD) event, an ESD tester generates an ESD event by providing an ESD test signal having a leading pulse and a trailing pulse. An ESD input of the device under test (DUT) receives the ESD test signal. An ESD protection circuit embedded in the DUT detects the ESD signal and asserts a trigger in response to the detection. The ESD protection circuit provides a leading discharge path to the leading pulse in response to detecting the ESD signal, thereby protecting the DUT during the leading pulse. In addition, the ESD protection circuit also provides a trailing discharge path to the trailing pulse in response to the trigger, thereby protecting the DUT during the trailing pulse.

REFERENCES:
patent: 5903220 (1999-05-01), Jon et al.
patent: 5946177 (1999-08-01), Miller et al.
C. Duvvury, R. Steinhoff, G. Boselli, V. Reddy, H. Kunz, S. Marum, R. Cline, “Gate Oxide Failures Due to Anomalous Stress from HBM ESD Testers”, EOS/ESD 2004, p. 132-140, no month.

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