Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2002-09-23
2004-08-17
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C377S033000
Reexamination Certificate
active
06778114
ABSTRACT:
FIELD OF THE INVENTION
The invention is directed toward the field of digital-to-analog converters (DACs) and delay-locked-loops (DLLs), and more particularly to DACs and DLLs based upon an escalator code.
BACKGROUND OF THE INVENTION
Recent integrated circuits attached to a printed circuit board (PCB) e.g., synchronous DRAM (SDRAM), RAMBUS DRAM, etc. include a delay-locked-loop (DLL) circuit. The DLL circuit maintains a predetermined phase relationship between an internal clock and an external reference or system clock, e.g., supplied by a memory controller.
In its simplest form, a DLL has a programmable delay line and some control logic. The delay line produces a delayed version of the reference clock signal. The delayed clock signal is provided to the other internal circuitry of the integrated circuit, e.g., the DRAM integrated circuit (IC), of which the DLL is a part. In addition to being provided to the other internal circuitry of the IC, the internal clock signal is also fed back to delay control logic of the DLL. The delay control logic compares the clock signal which has been fed back against the reference clock signal in order to adjust an amount of delay to be caused by the programmable delay line.
FIG. 1A
depicts a DLL according to the Background Art. The DLL
100
receives a reference clock, REFCLK, which is provided to a variable delay line
110
. The delayed clock signal, CLKOUT, is output to the remaining circuitry of the IC (not shown). The output clock signal CLKOUT is also fed back via replica delay unit
140
as signal FBCLK to a phase comparator
130
, which also receives the reference clock REFCLK. The phase comparator
130
provides an up/down-count signal to a delay control circuit (DCC)
120
. The DCC
120
includes a counter
122
which provides an N-bit output to an N-bit digital-to-analog converter (DAC). The DAC
121
, and therefore the DCC
120
, outputs a delay adjustment signal DLYADJ to the variable delay line
110
.
The function of the DLL
100
is to achieve a predetermined amount of phase difference between the reference clock signal REFCLK and the output clock signal CLKOUT. For the sake of simplicity, the operation of the DLL
100
will be explained under the assumption that the amount of predetermined delay is 360° or one cycle. The operation of the DLL
100
will now be discussed in terms of the waveforms of FIG.
1
B. In
FIG. 1B
, a waveform of the reference clock REFCLK is plotted. Below the REFCLK waveform, the feedback clock FBCLK waveform is plotted. As expected, the feedback clock FBCLK is delayed in phase, i.e., shifted to the right, relative to the reference clock REFCLK waveform. Recalling that the predetermined phase is assumed to be one cycle, arrows
160
-
168
have been provided to emphasize the delay between the rising edges of the feedback clock FBCLK waveform and the rising edges of the next respective cycle in the reference clock REFCLK waveform. Inspection of
FIG. 1B
reveals that the effect of the DLL
100
is to shorten the delays indicated by the arrows
160
-
168
.
The up-count waveform and down-count waveform of the phase comparator
130
are also depicted in FIG.
1
B. Each of the arrows
160
-
168
indicates that additional delay is needed, albeit in lesser amounts for waveform
160
through waveform
168
. Hence, the durations of the square pulses
170
-
178
in the up-count waveform diminish from pulse
170
through pulse
178
.
The phase magnitude between the feedback clock signal FBCLK in the reference clock signal REFCLK is also plotted in FIG.
1
B. Inspection of the phase (PH) waveform reveals that the magnitude of the phase difference decreases with the progression through the pulses
170
-
178
, as indicated by upward arrows
180
-
188
. Similarly, the delay adjust DLYADJ output by the N-bit DAC
121
increases inversely proportionally to the decrease in the phase difference. Similarly, the delay waveform, namely the waveform describing how close to a full cycle is the delay, decreases from left to right in correspondence to the decrease exhibited by the arrows
180
-
188
of the phase PH waveform.
The DAC
121
can be implemented in a number of ways. As simple implementation is to assign binary weighting to the individual transistors within the DAC
120
.
FIG. 3
is a schematic block diagram of a binary-weighted DAC
300
according to the Background Art. The DAC
300
includes four 1-bit converters
302
,
306
,
310
and
314
, which reflects an assumption of a 4-bit weighting system (the number four is chosen for simplicity; typical DACs involve more bits). The 1-bit converter
302
includes an output transistor
322
having a channel whose width-to-length (W/L) ratio is such that it produces a unit current of magnitude, i. The 1-bit converter
306
has an output transistor
324
whose channel has a width-to-length ratio of 2W/L that can sink a current of magnitude to 2i, i.e., twice that of the converter
302
. The 1-bit converter
310
has an output transistor
326
whose channel width-to-length ratio is 4W/L, which can sink a current of magnitude 4i. And the 1-bit converter
314
has an output transistor
328
whose channel width-to-length ratio is 8W/L, which can sink a current of magnitude 8i.
A binary system, like any positional number system, represents a number based upon the combination of individual bits, where each bit represents a sub-value based upon its relative position and whether it is in the zero state or the one state. A 4-bit binary number has bits b
3
b
2
b
1
b
0
, where b
0
=2
0
=1, b
1
=2
1
=2, b
2
=2
2
=4 and b
3
=2
3
=8, i.e., b
3
=8b
1
, b
2
=4b
1
and b
2
=2b
1
. Inspection of the 1-bit converters
314
,
310
,
306
and
302
reveals that their respective currents reflect a binary weighting for a 4-bit binary number.
The DAC
300
further includes a buffer
320
. One output
318
of the buffer
320
is connected to the inputs
304
,
308
,
312
and
316
of the 1-bit converters
302
,
306
,
310
and
314
, respectively. Based upon the control signals applied to each of the 1-bit converters, namely b
0
and b
0
b for converter
302
, b
1
and b
1
b for converter
306
, b
2
and b
2
b for converter
310
, and b
3
and b
3
b for converter
314
, each of the 1-bit converters is selectively turned on or off. When turned on, each 1-bit converter sinks its respective current. If all of the transistors are turned on, they collectively draw the sum of their individual currents out of the buffer
320
on the output line
318
. Similarly, the second output line
321
of the buffer
320
outputs the same amount of current as is drawn out of the output line
318
. The current on the second output line
321
represents the delay adjust signal DLYADJ.
FIG. 2A
is a depiction of an example amount of delay between the clock output CLKOUT of the DLL
100
and the reference clock REFCLK. Inspection of the waveform DLY reveals that it is a typical damping curve that settles down to a predetermined amount of delay
208
. It is to be noted that the output clock CLKOUT is an analog signal that can vary continuously. In contrast, the delay control circuit (DCC)
120
is a digital device that translates the up/down control signal from the phase comparator
130
into a binary-weighted word. Due to a variety of reasons, e.g., thermal fluctuation, system voltage fluctuations, noise, etc., there will be some oscillation or jitter
210
in the delay waveform DLY even after the DLL has achieved a locked state, i.e., after the waveform DLY settles at the predetermined amount of delay
208
. This jitter
210
falls within a range of values
220
. The locked status of the DLL
100
is shown as being achieved after 4 &mgr;sec.
FIG. 2B
is a depiction of 6-bit binary words and their decimal equivalent. To simplify the explanation, it is assumed that the jitter
210
corresponds to the count values 31
10
and 32
10
output by the counter
122
. In other words, it is assumed that the count values corresponding to the jitter
21
Harness & Dickey & Pierce P.L.C.
Samsung Electronics
Wamsley Patrick
LandOfFree
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