Errorless line protection switching in asynchronous transer mode

Details Errorless line protection switching in asynchronous transer mode Errorless line protection switching in asynchronous transer mode

1992-03-17

1994-02-08

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370108, 371 82, 340827, H04L 122

Patent

active

052854418

ABSTRACT:
An errorless line protection apparatus involves receipt of data from an active line and a standby line. A determination is made as to whether the data from the active line leads or lags the data on the standby line. A switching system directs the leading data to a lead channel containing a controllable amount of time delay up to the maximum amount that the leading data is expected to led the lagging data. Lagging data is directed to a lag channel. A selected one of the data from the lead channel or the lag channel is delivered to an output line.

REFERENCES:
patent: 4477895 (1984-10-01), Casper et al.
patent: 5051979 (1991-09-01), Chaudhuri et al.
patent: 5153578 (1992-10-01), Izawa et al.
C. P. Bates et al. "Effectiveness Of Error Correction And Errorless Frequency Diversity Switching In A Multipath Environment," IEEE Int'l Conf. on Communications '87, Seattle, Wash., USA, Jun. 7-10, 1987, pp. 0826-0830.

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