Error-suppressing phase comparator

Details Error-suppressing phase comparator Error-suppressing phase comparator

2000-03-20

2001-06-19

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S00100A, C331S014000, C331S025000, C331SDIG002, C327S012000, C327S007000, C327S156000, C327S159000

Reexamination Certificate

active

06249188

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an error-suppressing phase comparator which has a function of effectively reducing a phase error, for use particularly in a PLL circuit.
2. Description of the Related Art
FIG. 6
shows a prior art PLL circuit using a phase comparator
10
.
Received serial data DATA is a signal generated in synchronization with a reference clock on the transmission side. The reference clock is produced by a crystal oscillator, and its frequency changes within the maximum of about ±/100 PPM due to variations in temperature. Since the frequency fr of the reference clock is of a high value in the range of, for example, 500 MHz to 3 GHz, the value of the maximum variations is large and extends from ±/500 Hz to ±/3 MHz. Hence, using the PLL circuit as shown in
FIG. 6
, a clock signal CLK is recovered from the received serial data DATA.
When an edge of the recovered clock CLK leads an edge of DATA, the phase comparator
10
outputs a pulse of a down signal DOWN in order to delay the lead, while in the reverse situation, the phase comparator
10
outputs a pulse of an up signal UP. A charge pump
11
provides a pulse of a current signal depending on a pulse of the signal UP or DOWN. A loop filter
12
smoothes the current signal from the charge pump
11
, namely, filters out high frequency components to get a smoothed voltage signal, and the voltage signal is in turn applied to a voltage controlled oscillator (VCO)
13
. The VCO
13
generates clocks CLK and *CLK which are complementary to each other and whose frequency fc is in a linear relation with an input voltage thereto, and provides the clocks CLK and *CLK to the phase comparator
10
.
FIG. 7
shows the configuration of a prior art phase comparator
10
.
D flip-flops
14
and
15
latch DATA in response to rises of the recovered clocks CLK and *CLK and output data as B and U, respectively. D flip-flops
16
and
17
latch the B and U in response to the rise of the recovered clock CLK and output data as A and T, respectively. A determination circuit
18
is a combinational logic circuit and determines binary levels of the signals UP and DOWN depending on the values of A, T and B. The phase comparator with such a configuration is called a Bang Bang phase detector circuit (BBD).
FIGS.
8
(A) and
8
(B) are timing charts showing cases where the falling edge of the recovered clock CLK leads and lags the rising edge of DATA, respectively. FIGS.
9
(A) and
9
(B) are timing charts showing cases where the falling edge of the recovered clock CLK leads and lags the falling edge of DATA, respectively.
A, T and B respectively correspond to the values of DATA at three consecutive edges of the recovered clock CLK as shown in those figures. That is, T corresponds to the value of DATA on the falling edge of the CLK within −&pgr; to &pgr; relative to the edge of DATA, and A and B respectively correspond to the values of DATA on the preceding and succeeding rising edges of the CLK from that edge of DATA.
In a case where (A, T, B)=(‘0’, ‘0’, ‘1’) as shown in FIG.
8
(A), since the falling edge of the recovered clock CLK leads the rising edge of DATA, a pulse of the signal DOWN is generated in order to delay the lead. In
FIG. 7
, it means that in cases of TRISTATE where A, T and B are all ‘0’ or ‘1,’ a lead or lag of phase cannot be determined. VCO FAST indicates that the falling edge of the recovered clock leads the edge of DATA, which corresponds to a pulse of the signal DOWN. VCO SLOW indicates that the falling edge of the recovered clock lags the edge of DATA, which corresponds to a pulse of the signal UP. ERROR is a state that does not arises in the normal operation.
Since the phase comparator
10
of
FIG. 7
detects only lead or lag of phase, in a case where the phase comparator
10
of
FIG. 7
is employed in a PLL circuit, there is not sufficient follow-up control of the recovered clock to a reference clock. That is, if DATA are a number of ‘0s’ or ‘1s’ in sequence or a recovered clock frequency fc is largely shifted from the reference clock frequency fr, there arise an out of lock or an error in data got with timing of the recovered clock CLK.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an error-suppressing phase comparator in which follow-up control of a recovered clock to a reference clock is improved.
In one aspect of the present invention, there is provided an error-suppressing phase comparator comprising: a phase comparator circuit for activating a first or second signal depending on lead or lag, respectively, of one directional edge of a clock recovered from serial data, relative to an edge of the serial data; an overrun detector circuit for activating an overrun signal when detecting that the lead or lag exceeds a predetermined amount; and a modification circuit for outputting the first and second signals as down and up signals, respectively, when the overrun signal is inactive, and outputting signals corresponding to the first and second signals as the up and down signals when the overrun signal is active.
After the phase error becomes zero, the phase error increases owing to a pulse train of the down or up signal. However, with the present invention, when the phase error exceeds the predetermined amount, the phase err decreases by the up or down signal from the modification circuit, therefore follow-up control of the recovered clock to a reference clock is improved as compared with a prior art case.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.


REFERENCES:
patent: 5297173 (1994-03-01), Hikmet et al.
patent: 5619148 (1997-04-01), Guo
patent: 5789947 (1998-08-01), Sato
patent: 10-163757 (1998-06-01), None

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