Error signal generating arrangement

Details Error signal generating arrangement Error signal generating arrangement

2001-08-01

2003-04-01

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C714S795000

Reexamination Certificate

active

06542103

ABSTRACT:

The invention relates to an arrangement for generating an error signal, to an arrangement for generating a probability signal, and to a Viterbi decoder including such arrangements.
There is a continuing and increasing desire for larger data capacity on optical discs. Additionally, there is a desire for greater speed in reading the data from the disc. These two demands arise from the increasing use of optical storage media in video and high speed data applications and both these applications require performance far greater than that achieved in the original audio compact disc applications. As a result there is a demand for methodologies which allow for recovery of the data at rates which are at or near the limit achievable given the physics of the media, mechanics, optics, and electronics.
One of the consequences is an increasing level of inter-symbol interference in the data channel when reading data from the disc. The use of Viterbi decoders in reading data from optical discs has been disclosed in U.S. Pat. Nos. 5,661,709 and 5,450,389. These documents disclose arrangements in which the input signal is digitised in an A/D converter and all the manipulations are carried out in the digital domain. DVD systems currently being designed have the capability of decoding data at sixteen times nominal speed which represents a channel bit rate in excess of 400 Mb/s. As a result it requires very high speed digital signal processing leading to increased costs.
It is an object of the invention to enable the provision of a decoder, particularly, but not exclusively, for data read at high speed from an optical disc without requiring the use of high speed digital signal processors.
The invention provides an arrangement for generating an error signal representing the difference between an input signal voltage level at a sampling instant and an estimated value for the input signal voltage level, the arrangement comprising first and second transconductors, means for feeding the input signal to an input of the first transconductor, means for feeding the estimated value to an input of the second transconductor, and a differencing circuit for forming the modulus of the difference between the outputs of the first and second transconductors, the output of the differencing circuit providing the error signal.
A necessary part of a Viterbi decoder is a means for deriving the difference between an input signal and estimates of the valid values that the signal may have at the sampling instants. The arrangement described in the preceding paragraph enables an error signal to be determined which represents the modulus of the difference between these two values.
In an optical disc player and particularly in a DVD player, the physical aperture of the optical system is such that one bit period is much shorter than the total response of the photodiode system so inter-symbol interference occurs. In present laser optic recording there is a minimum number of consecutive “1s” or “0s” that are allowed in the data encoding (d-constraint). This number is currently three, that is in any data sequence must contain a minimum of three consecutive “1s” or three consecutive “0s”. This leads to a signal waveform that appears to be band limited but whose peak and trough levels are functions of the number of bits of the same value. The peak achieved with only three successive “1s” will be lower than if there are many successive “1s” (up to seventeen are allowed in the DVD standard). The sequences where only three successive bits have the same value, that is 01110 and 10001, are known as I3 states. As a result there are a number (in this case twelve, or eight if a symmetrical channel characteristic is assumed) of valid levels that the input signal may have depending on the sequence of bits being received. The arrangement described enables the error between the input signal voltage and estimates of the valid values to be obtained and subsequently used to determine the most likely data sequences.
The arrangement may further comprise a current subtractor for forming a probability signal, the probability signal representing the probability that the input signal is a signal of the estimated value, a reference current source being coupled to a first input of the subtractor and the error signal being coupled to a second input of the subtractor, the output of the subtractor providing the probability signal.
In this case where the input signal is compared with a number of estimates or reference levels an output is produced which increases in magnitude the closer the input signal level is to the estimate.
The input signal and the estimated value may both be differential signals, the first and second transconductors both being of differential form.
The arrangement may be such that the positive input signal and positive estimated value are applied to first and second inputs of the first transconductor and the negative input signal and the negative estimated value are applied to first and second inputs of the second transconductor.
This arrangement reduces the need for the two transconductors to have good linearity across the whole of their ranges as it results in the maximum probability condition occurring when the transconductors have zero differential input. As a result only the offset is significant and the linearity is less important.
Each transconductor may comprise a first long tail pair formed by two field effect transistors each having a channel width W1 and whose tail current is equal to I1 and a second long tail pair formed by two further field effect transistors each having a channel width W2 and whose tail current is equal to I2, wherein the drain electrodes of the two long tail pairs are cross connected, I1>I2, and W2>W1.
This results in the transconductance being lower in the centre region of the characteristic and rising towards the extremes thus giving an approximation to a square law characteristic.
The invention further provides a Viterbi decoder including a plurality of such arrangements.
The Viterbi decoding algorithm requires the determination of the magnitude of the errors between the incoming signal levels and the expected valid levels and the tracing of the possible level transitions through the allowable sequence of states. This process requires several manipulations of signals for each sample of input data to obtain certain metric values. These metric values are combined with stored values derived in previous sample periods. The manipulations include modulus subtraction, determination of the maximum of multiple inputs, and multiplication by constants. Further multiple signal paths are required in parallel. This leads to significant bottlenecks in the data flow in digital implementations. The present invention allows the modulus subtraction to be performed in the analogue domain using comparatively simple circuitry that can be easily replicated to create parallel signal processing paths.


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patent: 0658896 (1995-06-01), None

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