Error regulator circuit for sample and hold phase locked loops

Details Error regulator circuit for sample and hold phase locked loops Error regulator circuit for sample and hold phase locked loops

1996-01-11

1998-10-27

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327536, 327538, 331 17, H03L 706

Patent

active

058282548

ABSTRACT:
An error regulator circuit for use within a charge pump circuit of a phase-locked loop monitors levels of the control signals used to control the charge pump circuit. When one of the control signals remains at a predetermined voltage level for a predetermined period of time, indicating that the charge pump circuit is in a hold mode or an inactive period of time, the current sources within the charge pump used to charge and discharge a charge pump capacitor are temporarily disabled. During a hold or inactive period when one of the control signals used to control the charge pump circuit remains at the predetermined voltage level for more than a predetermined period of time, the current sources of the charge pump circuit are disabled and the charge pump circuit is prevented from charging or discharging the charge pump capacitor until the current sources are re-enabled, thereby allowing the charge pump circuit to maintain an appropriate level of charge across the capacitor during an inactive or hold period. The current sources are re-enabled when the control signal which was at the predetermined voltage level for more than the predetermined period of time is no longer at the predetermined voltage level.

REFERENCES:
patent: 4216388 (1980-08-01), Wilson
patent: 4414433 (1983-11-01), Horie et al.
patent: 4547741 (1985-10-01), Katakura
patent: 5095287 (1992-03-01), Irwin et al.
patent: 5148168 (1992-09-01), Masuda et al.
patent: 5223945 (1993-06-01), Honda et al.
patent: 5260979 (1993-11-01), Parker et al.
patent: 5272453 (1993-12-01), Traynor et al.
patent: 5304955 (1994-04-01), Atriss et al.
patent: 5362990 (1994-11-01), Alvarez et al.
patent: 5363326 (1994-11-01), Nakajima

Affiliated with

Also associated with

Rating

Error regulator circuit for sample and hold phase locked loops does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Error regulator circuit for sample and hold phase locked loops, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error regulator circuit for sample and hold phase locked loops will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1616377