Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-12-12
2004-12-07
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240, C365S185290
Reexamination Certificate
active
06829167
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to programming of nonvolatile erasable programmable memories and more specifically, a technique to recover data from unreadable nonvolatile memory cells, which will increase the reliability and longevity of the memory cells.
Memory and storage is one of the key technology areas that is enabling the growth in the information age. With the rapid growth in the Internet, World Wide Web (WWW), wireless phones, personal digital assistants (PDAs), digital cameras, digital camcorders, digital music players, computers, networks, and more, there is continually a need for better memory and storage technology.
A particular type of memory is the nonvolatile memory. A nonvolatile memory retains its memory or stored state even when power is removed. Some types of nonvolatile erasable programmable memories include Flash, EEPROM, EPROM, MRAM, FRAM, ferroelectric, and magnetic memories. Some nonvolatile storage products include Flash disk drives, CompactFlash™ (CF) cards, MultiMedia cards (MMC), secure digital (SD) cards, Flash PC cards (e.g., ATA Flash cards), SmartMedia cards, personal tags (P-Tag), and memory sticks.
A widely used type of semiconductor memory storage cell is the Flash memory cell. Some types of floating gate memory cells include Flash, EEPROM, and EPROM. There are other types of memory cell technologies such as those mentioned above. Floating gate memory cells such as Flash are discussed as merely an example. The discussion in this application would also apply to other memory technologies other than floating gate technology with the appropriate modifications.
Memory cells are configured or programmed to a desired configured state. In particular, electric charge is placed on or removed from the floating gate of a Flash memory cell to put the cell into two or more stored states. One state is a programmed state and another state is an erased state. A Flash memory cell can be used to represent at least two binary states, a 0 or a 1. A Flash memory cell can also store more than two binary states, such as a 00, 01, 10, or 11. This cell can store multiple states and may be referred to as a multistate memory cell, a multilevel, or multibit memory cell. This allows the manufacture of higher density memories without increasing the number of memory cells since each memory cell can represent more than a single bit. The cell may have more than one programmed state. For example, for a memory cell capable of representing two bits, there will be three programmed states and an erased state.
Despite the success of nonvolatile memories, there also continues to be a need to improve the technology. It is desirable to improve the density, performance, speed, durability, and reliability of these memories. It is also desirable to reduce power consumption and reduce the cost per bit of storage. One aspect of nonvolatile memories is the techniques used to recover data from memory cells which are unreadable or marginally readable.
As can be appreciated, there is a need for improving the circuitry and techniques for operating on memory cells.
BRIEF SUMMARY OF THE INVENTION
The invention is an error recovery technique used on marginal nonvolatile memory cells. A marginal memory cell is unreadable because it has a voltage threshold (VT) of less than zero volts. By biasing adjacent memory cells, this will shift the voltage threshold of the marginal memory cells, so that it is a positive value. Then the VT of the marginal memory cell can be determined. The technique is applicable to both binary and multistate memory cells.
During a typical or standard read mode, the adjacent memory cells are biased using a first VREAD voltage on their word lines. However, when it is desirable to recover data from a marginal memory cell in a recovery read mode, a second VREAD voltage is applied on the word lines of adjacent memory cells. This second VREAD voltage different from the first VREAD voltage. To shift the VT down, the second VREAD voltage is above the first VREAD voltage. Using the biasing technique, the VT may also be shifted up by using a VREAD voltage less than the first VREAD voltage. Depending on the magnitude of the difference between the first and second VREAD voltages, it will be possible to determine how much the VT of the marginal memory cell was shifted up, so the value of VT will be known. Then, the data stored in the marginal memory cell will be known.
This technology is based on a principle of adjacent word line (WL) coupling to floating gate (FG) effect. In previous generations of technologies, due to larger features and spacing, this coupling was negligible. The invention takes advantage of this coupling, due to scaling, to recover data.
After the data in the marginal memory cell is recovered, the data can be moved to another memory cell, and the marginal memory cell can be mapped so it is not used in the future. In a further embodiment of the invention, if there is a bad memory cell, the whole block where the bad memory cell was found will be moved to another location, and the block will not be used in the future.
In a specific embodiment, the invention is a method of operating a memory integrated circuit including providing a string of memory cells organized in a NAND structure.
A first memory cell in the string to read data from is selected. A VWL voltage is placed on a word line of the first memory cell. In an embodiment, VWL is ground. For a memory cell standard read mode, a first VREAD voltage is placed on a word line of a second memory cell, adjacent to the first memory cell. For a memory cell recovery read mode, a second VREAD voltage is placed on the word line of the second memory cell, wherein the second VREAD voltage is different from the first VREAD voltage. Data is read from the first memory cell.
In an embodiment, the second VREAD voltage is above or below the first VREAD voltage. In another embodiment, the second VREAD voltage is below the first VREAD voltage. VWL voltage is about zero volts. In an embodiment, the first VREAD voltage is in a voltage range from about 4 volts to about 5 volts. In another embodiment, the first VREAD voltage is in a voltage range from about 3 volts to 6 volts. In further embodiments, the first VREAD voltage may be less than 3 volts or greater than 6 volts. The second VREAD voltage is at least about 0.25 volts above or below the first VREAD voltage. The technique may further include for the memory cell recovery read mode, placing the second VREAD voltage on a word line of a third memory cell, also adjacent to the first memory cell, wherein the second VREAD voltage is different from the first VREAD voltage. The invention may be implemented using a controller of a storage device.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.
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“Notification of Transmittal of the International Search Report or the Declaration” corresponding to PCT/US03/39271, International Searching Authority, Europ
Chen Jian
Tu Loc
Elms Richard
Nguyen Hien
Parsons Hsue & de Runtz LLP
SanDisk Corporation
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