Error prevention circuit with capacitive means

Details Error prevention circuit with capacitive means Error prevention circuit with capacitive means

1989-03-17

1990-09-25

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307491, 307542, 307546, 307572, 307262, 3072964, 3072865, H03K 1716, H03K 301, H03K 19094

Patent

active

049595628

ABSTRACT:
A semiconductor integrated circuit equipped with an input buffer operation error prevention circuit is disclosed which comprises a data output signal level transition detector circuit for detecting at least one of a variation from a low level from a high level and a variation from a high level to a low level of a signal of a circuit of a stage preceding an output buffer and for generating a clock pulse and an input buffer signal terminal control circuit for controlling the terminal level of a first stage gate in an input buffer through the use of a clock pulse so as to cancel a fall in an input level detection margin of the input buffer which is caused when the output data of the output buffer varies from a "0" level to a "1" level and vice versa.

REFERENCES:
patent: 4290119 (1981-09-01), Masuda et al.
patent: 4833341 (1989-05-01), Watanabe et al.
Wada T. et al., "A 34ns 1MB CMOS SRAM Using Triple Poly", ISSCC Digest of Technical Papers, pp. 262, 263; Feb., 1987.
U.S. Patent Appln. Ser. No. 07/320,741 filed 3/8/89.

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