Error preventing circuit

Details Error preventing circuit Error preventing circuit

1989-03-08

1990-09-25

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307491, 307542, 307546, 307572, 307262, 3072964, 3072965, H03K 1716, H03K 301, H03K 19094

Patent

active

049595601

ABSTRACT:
A semiconductor integrated circuit equipped with an input buffer operation error preventing circuit is disclosed. A semiconductor integrated circuit comprises a data output signal level detector circuit for detecting at least one of a variation from a low level to a high level and that from a high level to a low level of a signal outputted from a circuit of a stage preceding an output buffer and for generating a clock pulse and an input buffer threshold level control circuit for controllably varying the threshold level of a first-stage gate in an input buffer by inputting the clock pulse so as to cancel a fall in an input level detection margin of the input buffer which is caused when the output data of the output buffer varies from a "0" level to a "1" level and vice versa.

REFERENCES:
patent: 4290119 (1981-09-01), Masudo et al.
patent: 4833341 (1989-05-01), Watanabe et al.
Wada et al., "A 34ns 1Mb CMOS SRAM Using Triple Poly", IEEE International Solid-State Circuits Conference, pp. 262-263, Feb. 1987.

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