Error management processes for flash EEPROM memory arrays

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371 214, 371 216, G06F 1100

Patent

active

054756936

ABSTRACT:
A method of utilizing circuitry including error detecting and correcting circuitry to detect and correct errors which can occur in data stored in multi-bit per cell format in a flash EEPROM memory array before those errors can affect the accuracy of data provided by a flash EEPROM memory array.

REFERENCES:
patent: 5200959 (1993-04-01), Gross et al.
patent: 5274646 (1993-12-01), Brey et al.

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