Excavating
Patent
1994-08-05
1996-02-27
Beausoliel, Jr., Robert W.
Excavating
39518510, 39518310, 39518322, 371 216, 371 61, G11C 2900
Patent
active
054955734
ABSTRACT:
An error logging system where errors are captured on dual system busses operating at a lower clock rate (16 MHz) than the processor which receives the error information. The system functions to substantially reduce the loads on the processor in addition to maximizing the use of the system bus drivers which are pin-constrained. The processor operates at a higher clock rate (32 MHz). Processor commands to read error data from an error log register are synchronized down to the 16 MHz rate, then enabled onto a processor bus after a second synchronization operation back to the higher (32 MHz) rate. Provision is made for identifying several different types of error categories. An expandable error log register system is provided which uses selected bit positions to identify types of errors logged to the processor which also enables expansitivity for adding in future types of errors into the error logging system and renders compatibility for a processor operating at first clock rate with error data sensed at a second clock rate.
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Datwyler Wayne C.
Ha Long V.
Tran Dan T.
Axenfeld Robert R.
Beausoliel, Jr. Robert W.
Kozak Alfred W.
Le Dieu-Minh
Starr Mark T.
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