Error logging memory system for avoiding miscorrection of triple

Details Error logging memory system for avoiding miscorrection of triple Error logging memory system for avoiding miscorrection of triple

1984-06-29

1986-08-05

Fleming, Michael R.

Excavating

371 21, G06F 1110

Patent

active

046047514

ABSTRACT:
Miscorrection of triple errors is avoided in a memory system equipped with a single bit error detection and correction/double bit error detection code by providing a double bit error logging technique. The address of each fetched word is logged in which a double bit error is detected. The address of each fetched word in which a single bit error is detected is compared with all logged addresses. If a coincidence is found between the compared addresses, a triple bit error alerting signal is generated and error recovery procedures are initiated.

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