Error information saving apparatus of computer

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3642473, 3642318, 364265, G06F 1100

Patent

active

052838919

ABSTRACT:
An error information saving apparatus of a computer includes at least one arithmetic unit, a plurality of storage units, and a control unit, connected to the storage units and the arithmetic unit, for controlling these units to perform a predetermined pipeline operation, wherein the storage units comprise an arithmetic register file consisting of a plurality of registers each of which can be designated as a destination operand in a statement of an operation instruction, a status flag string consisting of a plurality of flags provided in a one-to-one correspondence with the registers of the arithmetic register file, and a destination register number holding unit for sequentially saving and holding the numbers of destination registers of all operations performed while error interrupt processing generated after occurrence of an error is delayed by a predetermined time interval, each time one of the operations is completed.

REFERENCES:
patent: 4443849 (1984-04-01), Ohwada
patent: 4701915 (1987-10-01), Kitamura et al.
patent: 4811283 (1989-03-01), Gembarowski

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