Error handling mechanism for a controller having a plurality of

Details Error handling mechanism for a controller having a plurality of Error handling mechanism for a controller having a plurality of

1992-09-29

1995-06-06

Atkinson, Charles E.

G06F 1134

Patent

active

054230250

ABSTRACT:
An error handling and reporting mechanism is capable of taking advantage of sophisticated error analysis performed after clocks have been stopped in response to an error detected in a controller. The controller provides services in a data processing system in response to requests for controller services from a plurality of requestors. The controller includes a plurality of ports for storing requests for controller services. A plurality of servers is coupled to the plurality of ports, and perform separate services associated with the requests for controller services stored in the plurality of ports. An error reporting mechanism is included which is responsive to a detected error in a particular server associated with a request in a particular port, for posting error status in the particular port and causing clock stoppage within a clock stop latency period. An error analysis mechanism analyzes the detected errors during the clock stoppage. Error handling logic is coupled with the error analysis mechanism, and is responsive to the posted error status in the ports, for notifying a requestor of an error status posted with a request in the particular port. The error handling logic includes a stall counter, which stalls the error handling mechanism in response to the posted error status for at least the clock latency period so that the clock stoppage occurs and the error analysis mechanism completes error analysis before the requestor is notified.

REFERENCES:
patent: 4604746 (1986-08-01), Blum
patent: 4982402 (1991-01-01), Beaven et al.

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