Error display system

Details Error display system Error display system

1991-10-28

1994-12-27

Cosimano, Edward R.

Excavating

G06F 1520

Patent

active

053772040

ABSTRACT:
An error display system applied to a control circuit of data communication includes a first first-in-first-out buffer memory and a second first-in-first-out buffer memory. Communication data providing one frame with a plurality of words of which one word is formed of one bit, are sequentially stored for reading out the communication data in the sequence in which it is stored in the first first-in-first-out buffer memory. Last word data and error display data composed of two bits are inputted in the second first-in-first-out buffer memory. One of the two bits represents the last word of the one frame of the communication data and the other bit represents the presence of an error existing within the one frame of the communication data. The first first-in-first-out buffer memory has a larger capacity than that of the one frame.

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patent: 5003508 (1991-03-01), Hall
patent: 5170466 (1992-12-01), Rogan et al.
patent: 5287458 (1994-02-01), Michael et al.

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