Error detector circuit and method therefor

Details Error detector circuit and method therefor Error detector circuit and method therefor

1993-05-20

1995-05-09

Canney, Vincent P.

Excavating

371 381, 375324, H04L 2722

Patent

active

054147115

ABSTRACT:
An error detector circuit and associated method for a digital receiver. The digital receiver is operative in a TDMA communication scheme in which DQPSK-modulated signals are generated, such as the Japanese Digital Cordless Telephone System. The error detector circuit detects times in which an excessive amount of noise or other distortion is introduced upon one or more sequences of a signal transmitted during one or more time slots in the TDMA communications scheme. A receiver incorporating the error detector circuit is operative not to decode portions of a received signal when excessive numbers of sequences include excessive amounts of noise or other distortion introduced thereupon. Thereby, degradation of the audio quality of a signal actually recreated by the receiver incorporating the error detector.

REFERENCES:
patent: 5272446 (1993-12-01), Chalmers et al.

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