Error detection system

Details Error detection system Error detection system

1987-12-15

1989-12-19

Atkinson, charles E.

Excavating

G06F 1110

Patent

active

048887749

ABSTRACT:
An error detecting apparatus in which an error within an arbitrary and continuous (b-1) bit block is detected using a SEC-DED-SbED code. The (b-1) bit block is any continuous (b-1) bit block within an information consisting of several b bit blocks. The data are encoded by using a power of a matrix C, defined as: ##EQU1## and a matrix B. Matrix B is comprised by arbitrarily replacing the rows and columns of the power of C matrix with row vectors from a set of (b+1) vectors: ##EQU2## The partial matrices obtained from matrices B and C are used to construct a parity matrix. Syndromes are computed from the information and the party matrix to detect errors.

REFERENCES:
patent: 4359772 (1982-11-01), Patel
patent: 4450561 (1984-05-01), Gotze et al.
patent: 4692922 (1987-09-01), Kiriu et al.
"Error Correcting Codes for SemiConductor Memory Applications: A State of the Art Review" by C. L. Chen and M. Y. Hsiao.

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