Error detection structure and method for serial or parallel data

Details Error detection structure and method for serial or parallel data Error detection structure and method for serial or parallel data

1994-06-14

1997-01-28

Beausoliel, Jr., Robert W.

Excavating

371 51, G06F 1100

Patent

active

055984240

ABSTRACT:
The present invention provides a means and method of generating a long error checking polynomial remainder having the ability to detect errors with high reliability and inserting only a subset of the polynomial remainder periodically into a data stream, then at the receiving end recalculating the polynomial remainder and checking the inserted subset for errors. The polynomial has the property that the current remainder value is a function of all data previously transmitted in a transmission session. The subset transmitted also preferably has this property. A longer subset of the polynomial remainder, or the full polynomial remainder, may be inserted less frequently, and is preferably sent and tested at the end of the transmission session. Both serial and parallel data streams may be checked.

REFERENCES:
patent: 4208650 (1980-06-01), Horn
patent: 4276646 (1981-06-01), Haggard et al.
patent: 4507782 (1985-03-01), Kunimasa et al.
patent: 4594711 (1986-06-01), Thatte
patent: 4706216 (1987-11-01), Carter
patent: 4723244 (1988-02-01), Iacoponi
patent: 4870302 (1989-09-01), Freeman
patent: 4964124 (1988-12-01), Burnett
patent: 5140595 (1992-08-01), Geldman et al.
Xilinx Programmable Gate Array Data Book, 1989, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
Swanson, Robert; "Understanding Cyclic Redundancy Codes", pp. 93-99, Computer Design, Nov. 1975.
IEEE Transactions On Communication Technology, vol. 38, No. 1, Jan. 1990, New York, pp. 111-114, XP102585, Castagnoli et al., "Optimum Cyclic Redundancy-Check Codes With 16-Bit Redundancy".

Affiliated with

Also associated with

Rating

Error detection structure and method for serial or parallel data does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Error detection structure and method for serial or parallel data, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error detection structure and method for serial or parallel data will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-945954