Error detection in the basic processing unit of a VLSI central p

Details Error detection in the basic processing unit of a VLSI central p Error detection in the basic processing unit of a VLSI central p

1990-10-09

1993-11-16

Baker, Stephen M.

Excavating

395575, G06F 1116

Patent

active

052630340

ABSTRACT:
In order to provide efficient error detection in a central processor's Basic Processing Unit (BPU) including an AX (address and execution) module, a DN (decimal numeric) module and an FP (floating point) module, each module is provided redundantly in a master/slave pair, and the local result of data manipulation operations performed in each pair are compared for identity before the results are validated for subsequent use in the central processor.

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