Error detection for parallel data transfer between a processor a

Details Error detection for parallel data transfer between a processor a Error detection for parallel data transfer between a processor a

1993-02-10

1996-04-09

Nguyen, Hoa T.

Excavating

39518505, 371 53, 371 376, 371 377, G06F 1100, G06F 1130

Patent

active

055069584

ABSTRACT:
A method and apparatus for performing error detection on data transfer through a parallel interface port at a substantially increased data transfer rate with a minimum of handshaking. Blocks of data are transferred between a sending device and a receiving device, and each of the respective devices maintains a checksum. Each checksum comprises an initial value, and added to that value is the value of each data byte transferred through the parallel port interface. After a block of data bytes has been transferred, the checksum maintained by the sending device and the receiving device are compared. If the checksums are equal, no error is assumed to have occurred during the data transfer. If the checksums are not equal, an error is assumed to have occurred during the data transfer, and the data is retransferred with the previously transferred block discarded.

REFERENCES:
patent: 4148098 (1979-04-01), McCreight et al.
patent: 4413339 (1983-11-01), Riggle et al.
patent: 4451884 (1984-05-01), Heath et al.
patent: 4864652 (1989-09-01), Austin et al.
patent: 5058110 (1991-10-01), Beach et al.

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