Error detection circuitry for digital systems

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G06F 1110

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active

045077835

ABSTRACT:
Circuitry for detecting errors in a digital bit stream comprising a succession of data blocks and wherein each data block incorporates a parity check. At an error monitoring location, a bistable device toggles in response to either a logical "1" or "0" in the bit stream. The output of the bistable device is sampled at a submultiple of the bit rate and compared with a predetermined criterion to detect bit errors.

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patent: 4412329 (1983-10-01), Yarborough, Jr.
patent: 4425645 (1984-01-01), Weaver et al.
D. R. Hill, "140 Mb/s Optical Fiber Field Demonstration System", Electrical Communication, vol. 54, No. 1, Nov. 1, 1979.

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