Error detection circuit for power up initialization of a memory

Details Error detection circuit for power up initialization of a memory Error detection circuit for power up initialization of a memory

1994-01-31

1996-11-12

Beausoliel, Jr., Robert W.

Excavating

39518318, 371 212, G06F 1134

Patent

active

055748570

ABSTRACT:
A circuit for testing the accuracy with which data is written from a first memory cell to a second memory cell including a shift register including master and slave portions, apparatus for placing data from the first memory cell into the master portion of the shift register and shifting the data into the slave portion of the shift register, apparatus for placing the data from the first memory cell into the second memory cell, apparatus for placing the data in the second memory cell back into the master portion of the shift register, and logic circuitry for testing the condition of the data in the master portion of the shift register against the condition of the data in the slave portion of the shift register to determine if the data has been correctly written into the second memory cell.

REFERENCES:
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patent: 5166936 (1992-11-01), Ewert et al.
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patent: 5210865 (1993-05-01), Davis et al.
patent: 5343436 (1994-08-01), Suzuki
patent: 5359569 (1994-10-01), Fujita et al.
patent: 5381418 (1995-01-01), Montoye
patent: 5396619 (1995-03-01), Walton
patent: 5430687 (1995-07-01), Hung et al.

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