Boots – shoes – and leggings
Patent
1987-07-02
1989-09-26
Fleming, Michael R.
Boots, shoes, and leggings
371 53, G06F 1110
Patent
active
048706078
ABSTRACT:
In an error detection circuit for use in combination with a logic unit to detect an error by monitoring a binary signal of k bits in a logic circuit which carries out a predetermined operation with respect to a modulus number, where m is equal to 2.sup.k -1, zeroth through (m-1)-th codes are assigned to the predetermined operation while an m-th code is prepared as a specific code to monitor and to detect an error in the error detection circuit. The logic circuit may be either one of a modulo-m register circuit, a modulo-m coincidence circuit, and a modulo-m calculation circuit. Alternatively, at least two of the modulo-m circuits may be combined to form the logic circuit. If m=3, the specific code may be (1, 1).
REFERENCES:
patent: 3602704 (1971-08-01), Akushsky
patent: 3816728 (1974-06-01), Chen
patent: 3873820 (1975-03-01), Parr
patent: 4181969 (1980-01-01), Smith
G. G. Landon Jr. et al, "Concurrent Error Detection for Group Look-ahead Binary Adders," IBM Journal of Research and Development, Sep. 1970, pp. 563-573.
F. F. Sellers, Jr. et al, "Error Detecting Logic for Digital Computers," McGraw Hill Co., Inc., New York, 1968, pp. 41-45 and pp. 76-80.
Fleming Michael R.
NEC Corporation
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