Patent
1996-06-07
1999-06-22
Palys, Joseph E.
G06F 1108
Patent
active
059150823
ABSTRACT:
A lockstep processor system adds error detection, isolation, and recovery logic to one or more lockstep processor system functions; namely, control outputs, processor inputs, I/O busses, memory address busses, and memory data busses.
REFERENCES:
patent: 4438494 (1984-03-01), Budde et al.
patent: 4503535 (1985-03-01), Budde et al.
patent: 4823256 (1989-04-01), Bishop et al.
patent: 4916704 (1990-04-01), Bruckert et al.
patent: 5138708 (1992-08-01), Vosbury
patent: 5226152 (1993-07-01), Klug et al.
patent: 5233615 (1993-08-01), Goetz
patent: 5249187 (1993-09-01), Bruckert et al.
patent: 5249188 (1993-09-01), McDonald
patent: 5255367 (1993-10-01), Bruckert et al.
patent: 5313575 (1994-05-01), Beethe
patent: 5339408 (1994-08-01), Bruckert et al.
patent: 5353436 (1994-10-01), Horst
patent: 5640521 (1997-06-01), Whetsel
Langston Dale G.
Marshall Joseph R.
Elisca Pierre E.
Lockheed Martin Corporation
Palys Joseph E.
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