Error detection and correction system for use with address trans

Details Error detection and correction system for use with address trans Error detection and correction system for use with address trans

1995-12-14

1998-05-12

Baker, Stephen M.

Excavating

371 401, 39518204, 39518506, H03M 1300, G06F 1110

Patent

active

057517401

ABSTRACT:
A data transmission system for use in a mass memory system includes a unique EDAC which corrects all single component errors and detects all double component errors. High speed operation permits use of the EDAC on address and control lines as well as on data lines. In memory systems which use virtual memory addressing, further efficiency and economy is achieved by incorporating a partial implementation of the EDAC encoding in the same virtual memory address translation unit in which virtual memory address are calculated. False indications of error are avoided by ANDing the signals which indicate the location of an error, with an inclusive OR of all the bits which indicate the existence of an error but not the location of the error. In such manner, the error location signals are set to zero when the error detection bits indicate that there are no errors.

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