Error detection and correction system

Details Error detection and correction system Error detection and correction system

1984-12-13

1987-02-24

Smith, Jerry

Excavating

371 13, 371 37, G06F 1100

Patent

active

046463127

ABSTRACT:
An error detection and correction apparatus including a transmission bus for transmitting multi-bit data signals and multi-bit error correction code signals generated responsive to the multi-bit data signals in accordance with a modified Hamming code technique. Parity generators are connected to the bus for receiving the bits of the data signals and selected bits of the error correction code signals in accordance with the modified Hamming code technique for determining if a single bit error exists in the data. A two-state comparison gate is connected to the parity generators which has a first state if a single bit error does exist, and a second state if a single bit error does not exist. A separate error detection and correction circuit is provided to detect and correct any single bit errors in the data on the transmission bus. The two-state comparison gate is reset to its second state after the separate error detection and correction circuit corrects any single bit error in the data.

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