Error detection and correction scheme for main storage unit

Details Error detection and correction scheme for main storage unit Error detection and correction scheme for main storage unit

1987-06-11

1989-07-25

Atkinson, Charles E.

Excavating

G06F 1110

Patent

active

048521000

ABSTRACT:
The present invention provides an apparatus for reporting errors in data stored in a memory apparatus of a data processor, comprising: first means for storing multiple digital first signals; second means for storing said multiple digital first signals and adapted for storing at least one digital second signal; third means for transmitting said multiple digital first signals substantially from said first means to said second means; fourth means for providing said at least one digital second signal, in the course of the transmitting of said first signals by said third means, in response to an occurrence of one or more errors in one or more of said multiple digital first signals; fifth means for transmitting said multiple digital first signals substantially from said second means to said first means; and sixth means adapted for receiving said at least one digital second signal in the course of the transmitting of said multiple digital first signals by said fifth means and for providing at least one third signal in response to an occurrence of said at least one digital second signal. ECC codes are generated and applied over a plurality of distinct checking blocks in each flow of data in order to minimize delays in the move-in data path, and bypass data paths are provided such that a flow may bypass all error checking and correcting circuitry and cacheing apparatus between the main storage array and the CPU.

REFERENCES:
patent: 3218612 (1965-11-01), Sorg, Jr. et al.
patent: 3825893 (1974-07-01), Bossen et al.
patent: 3836957 (1974-09-01), Duke et al.
patent: 4077565 (1978-03-01), Nibby, Jr. et al.
patent: 4112502 (1978-09-01), Scheuneman
patent: 4393502 (1983-07-01), Tanaka et al.
patent: 4456996 (1984-06-01), Haas et al.
patent: 4712216 (1987-12-01), Glaise
patent: 4745604 (1988-05-01), Patel et al.

Affiliated with

Also associated with

Rating

Error detection and correction scheme for main storage unit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Error detection and correction scheme for main storage unit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error detection and correction scheme for main storage unit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2364236