Error detection and correction in data processing systems

Communications: electrical – Digital comparator systems

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235153AM, G06F 1110

Patent

active

040054055

ABSTRACT:
An error detection and correction system for use in a data processing system wherein all single bit errors in a data word can be detected and corrected by the use of a unique modified Hamming code technique. In accordance therewith, during the write portion of a memory cycle, odd and even parity checks are made on a predetermined number of different, selected combinations of bits in each data word, to form a plurality of parity check bits which are combined with the original data word bits to form an extended data word. During the read portion of the memory cycle, the same number of odd and even parity checks are made on selected combinations of bits of the extended data word which combinations include the same selected combinations of bits used during the write portion plus the parity check bit associated therewith to provide a plurality of error bits. The error bits are decoded to identify the location of any single-bit error which may have occurred in the extended data word so that the bit in such location can be corrected.

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