Error detection and correction for four-bit-per-chip memory syst

Details Error detection and correction for four-bit-per-chip memory syst Error detection and correction for four-bit-per-chip memory syst

1995-10-03

1998-05-26

Baker, Stephen M.

Excavating

371 404, 371 4012, 371 4017, H03M 1300

Patent

active

057578230

ABSTRACT:
Advantage is taken of the presence of identity submatrices in a parity check matrix to achieve correction of errors in a single symbol and detection of errors in a single symbol together with a single bit error in another symbol for use in computer memory systems. The code structure enhances utilization of chip real estate and specifically provides for the utilization of a (76,64) code which employs 19 chips per computer memory word as opposed to 20 chips per word.

REFERENCES:
patent: 4961193 (1990-10-01), Debord et al.
Bossen, "b-Adjacent Error Correction", IBM Journal of Research and Development, Jul. 1970, pp. 402-408.
Chen, "Symbol Error-Correcting Codes for Computer Memory Systems", IEEE Transactions on Computers, vol. 41, No. 2, Feb. 1992, pp. 252-256.

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