Excavating
Patent
1993-07-13
1995-03-28
Gordon, Paul P.
Excavating
371 376, G06F 1100
Patent
active
054024293
ABSTRACT:
The error detection and correction device detects and corrects single bit errors in a sequence of bits comprising a plurality of n-bit containing subsets applied on a parallel bus IN having m subset parts. It includes a storage module ST connected to the bus IN and which transfers the subsets as they are received on the bus to a divider logic circuit DL. This circuit performs a m*n bit parallel modulo 2 division of the received sequence by a given polynomial and transfers the remainder REM to a comparison circuit C where it is compared with a zero byte or with an error code byte HEC contained in the sequence depending on the position of the first byte of the sequence on the bus. Based on the result of the comparison and using translation tables a processor circuit PR determines the bit position in the sequence of a bit error. A correction logic CL corrects the received sequence.
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AN 92-032940 C05!, Derwent Publications Ltd., London, GB, Week 9205 and AU-D-7 704 291, Dec. 5, 1991 (Alcatel N.V.).
Patent Abstracts of Japan, vol. 16, No. 188 (E-1198) May 7, 1992 and JP-A-40 23 646 Jan. 28, 1992 (NIC Corp.).
Patent Abstracts of Japan, vol. 15, No. 284 (E-1091) Jul. 18, 1991 and JP-A-30 98 346 Apr. 23, 1991 (NTT Corp.).
ALCATEL N.V.
Gordon Paul P.
Moise Emmanuel L.
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