Error detection and correction apparatus for an asynchronous tra

Details Error detection and correction apparatus for an asynchronous tra Error detection and correction apparatus for an asynchronous tra

1997-08-05

1999-10-05

Marcelo, Melvin

Multiplex communications

Data flow congestion prevention or control

Control of data admission to the network

370233, 370395, H04L 1256

Patent

active

059635436

ABSTRACT:
An adaptive error detection and correction apparatus for an Asynchronous Transfer Mode (ATM) network device comprises a sensing unit for sensing a congestion condition in the ATM network and a global pacing rate unit for adaptively reducing a maximum allowable transmission ratio of ATM cells containing information to idle ATM cells in response to a sensed congestion condition. A processor stores a number corresponding to a relatively high maximum allowable transmission ratio in the global pacing rate register in the absence of a sensed congestion condition, and stores a number corresponding to a relatively low maximum allowable transmission ratio in the global pacing rate register in response to a sensed congestion condition. A controller adjusts the maximum allowable transmission ratio in accordance with the number stored in the global pacing rate register. A plurality of peak pacing rate counters reset to predetermined values upon decrementation to zero, the predetermined values corresponding to service intervals for segmentation of Conversion Sublayer Payload Data Unit (CD-PDU)s. The processor further includes circuitry for assigning the counters to selected CD-PDUs, and sensing the counters to determine whether or not segmentation of the selected CD-PDUs is within the respective service intervals. The apparatus further includes a channel group credit register having bits corresponding to the respective counters.

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