Error detection and correction apparatus for a logic array

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371 57, G06F 1100

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active

044184107

ABSTRACT:
Error detection and correction apparatus for a programmable logic array (PLA) having AND and OR logic combinations merged therein is disclosed. The output lines from the AND and OR logic elements are coupled in such a manner that their functions form complete groups containing, if possible, all minterms. Missing minterms are added, as necessary, by special output lines or logic elements provided for that purpose to complete a group. If a minterm occurs on two or more function lines, the corresponding minterm is entered as a correction term into an error detection logic means, one of which is associated with each group of logic output lines. The error detection logic means are also utilized to test whether one, and only one, of the output lines in a grouping of function lines has a binary 1 value.
Error correction signals are generated by mixed group error detection means, the inputs of which are connected to a function line of another function group. If a single error is detected, the error detection logic means for the function line groups indicate which group includes the erroneous function line. The mixed group error detection means similarly indicate, if appropriate, which of function lines of the mixed group is erroneous.

REFERENCES:
patent: 3958110 (1976-05-01), Hong et al.
patent: 4020460 (1977-04-01), Jones et al.
patent: 4140967 (1979-02-01), Balasubramanian et al.
patent: 4225957 (1980-09-01), Doty, Jr. et al.
Curlander, "Logic Array Checking" IBM Tech. Disclosure Bulletin vol. 18, No. 7, Dec. 1975, pp. 2044-2046.
Cha, "Testing of Programmable Logic Array Cross-Point Defects" IBM Tech. Disclosure Bulletin vol. 18, No. 8, Jan. 1976 pp. 2737-2739.
Logue et al "Programmable Logic Array Error Detection and Error Correction" IBM Tech. Disclosure Bulletin vol. 19, No. 2, Jul. 1976, pp. 588-590.

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