Error detecting/correction code and apparatus

Details Error detecting/correction code and apparatus Error detecting/correction code and apparatus

1988-03-02

1990-09-18

Smith, Jerry

Excavating

371 371, 371 491, G06F 1110

Patent

active

049583506

ABSTRACT:
A method and apparatus for detection and correction of errors in binary coded information. The method involves receiving a word of binary coded information and grouping the bits of the word of information. Parity bits are generated for each of the groups of bits. The bits are grouped according to three rules: (1) for any three parity bits, there is either one data bit or no data bit whose value effects all three parity bits, (2) for any four parity bits, there is no data bit whose value effects all four, and (3) for any data bit, there are exactly three parity bits whose values are effected by its value. The word bits and parity bits are stored on memory circuits. The bits are stored on the memory circuits in accordance with three rules: (1) no memory circuit may have both data bits and parity bits stored on it, (2) for all bits on a data chip, the sets of parity bits affected by them intersect in one parity bit, (3) for all parity chips, no data bit effects the value of three bits on the chip. A second set of parity bits are generated based on bits read from memory. From this second set of parity bits it is determined whether an error has occurred and whether the error is correctable. The present invention is capable of correcting all single bit errors and detecting two-bit errors or single memory circuit failures.

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patent: 4464747 (1984-08-01), Groudan
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patent: 4696007 (1987-09-01), Moriyama
patent: 4775978 (1988-10-01), Hartness
patent: 4780809 (1988-10-01), Woffinden
patent: 4785452 (1988-11-01), Petz
patent: 4809278 (1989-02-01), Kim

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