Error detecting circuit in a line length decoding system

Details Error detecting circuit in a line length decoding system Error detecting circuit in a line length decoding system

1999-08-05

2001-03-13

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

With error detection or correction

C341S067000, C382S246000, C358S426010

Reexamination Certificate

active

06201487

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of The Invention
The present invention concerns an error detection circuit in a line length decoding system, and more particularly an error detection circuit for detecting errors of decoded data by comparing the states of the data streams in data blocks when decoding data in real time.
2. Technical Background
In the conventional line length decoding system, the error detection circuit generates an absolute address based on the level of the image data and the run representing the number of zeros (‘0’s) in the image data, and stores it into the memory upon detecting end-of-block (EOB) signal, so that the absolute address is compared to a reference address to generate a digital coefficient signal to detect the bit errors. Hence, the error propagation caused by the successive bit errors is detected to stop the decoding operation, stabilizing the signal processing.
Referring to
FIG. 1
, the conventional error detection circuit comprises a signal processor
110
, first-in first-out (FIFO) device
120
, registers
131
,
132
,
133
, up counter
140
, comparators
151
and
152
, AND gate
160
, OR gate
170
, and error detector
180
. The error detector
180
includes a NAND gate
181
with two inputs receiving the output of the register
131
, a NAND gate with two inputs receiving the output of the up counter
140
, and an AND gate with two inputs respectively receiving the outputs of the two NAND gates
181
and
182
.
In operation, the signal processor
110
accumulates the level of a compressed image data externally inputted and the runs representing the number of ‘0’s in the image data to transfer the absolute address represented by the accumulated value and the inputted level to the FIFO device
120
according to the EOB signal. In addition, the signal processor
110
decodes the compressed image data into the original data. The EOB signal is to indicate that the image data inputted to the signal processor
110
by blocks is positioned in the last block. Then, the FIFO device
120
transfers the absolute address and level to the registers
131
and
132
according to the read signal generated from the AND gate
160
. The register
131
transfers the absolute address to the comparators
151
and
152
and the error detector
180
. Likewise, the register
132
transfers the level to the AND gate
160
.
The up counter
140
transfers the reference address to the comparators
151
,
152
and error detector
180
to determine whether the data is correctly decoded by the signal processor
110
. Namely, the comparators
151
and
152
compare the absolute address from the register
131
with the reference address from the up counter
140
to determine whether the data has been correctly decoded by the signal processor
110
, transferring the resultant signal to the OR gate
170
, which logically combines the output signals of the comparators
151
and
152
to generate an output supplied to the AND gate
160
. Then, the AND gate
160
logically multiplies the level from the register
132
and the output of the OR gate
170
to generate an output signal supplied to the FIFO device
120
and registers
131
,
132
and
133
. In this case, when the data decoded by the signal processor
110
conforms with the original data, it transfers the read signal to the FIFO device
120
and registers
131
and
132
while transferring the level to the register
133
. Meanwhile, the error detector
180
detects the errors occurring in the data decoded by the signal processor
110
based on the absolute address from the register
131
and the reference address from the up counter
140
.
Generally, when decoding in real time the data compressed by the variable length coding, an incorrectly inputted run value displaces the positions of the generated coefficients to make the synchronization of the coefficients mismatched, so that the time taken for processing data is increased or processing errors occur. In order to resolve such problems has been used the above described error detection circuit in the line length decoding system. However, such error detection circuit requires additionally a number of registers to store the absolute address and level generated according to the run, level and EOB signal, complicating its structure. Further, since the signals processed must be read and written by the many registers, the signal processing time is too much consumed to apply it to a high speed decoding system.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a line length decoding system with a error detection circuit, which employs a minimum number of logic gates to detect errors occurring in a decoded data by comparing the states of the data streams block by block, so that its structure is not only simplified, but also the signal processing speed is considerably improved.
According to the present invention, an error detection circuit for detecting errors occurring in a data obtained by decoding a compressed image data block by block in a line length decoding system, comprises a first storage device for temporarily storing the run representing the number of zeros (‘0’s) in the compressed image data and an EOB signal externally inputted, a selection signal generator for generating a first and a second selection signal in response to the EOB signal supplied from the first storage device, a first selection circuit for selectively transferring the run supplied by the first storage device or ground signal according to the first selection signal, a second selection circuit for selectively transferring the run supplied by the first storage device or ground signal according to the second selection signal, a reference value generator for generating a reference value based on the output signal of the first selection circuit according to an operation control signal externally inputted, accumulator for accumulating the output of the second selection circuit based on the feedback signal from a second storage device, the second storage device temporarily storing the output of the accumulator, and an error detector for detecting the errors based on the reference value and the output of the second storage device.
The present invention will now described more specifically with reference to the drawings attached only by way of examples.


REFERENCES:
patent: 5007102 (1991-04-01), Haskell
patent: 5264848 (1993-11-01), McGuffin
patent: 5694127 (1997-12-01), Tayama
patent: 5764357 (1998-06-01), Dockser
patent: 6069575 (2000-05-01), Kinouchi et al.
Dave Galbi et al., “An MPEG-1 Audio/Video Decoder with Run-Length Compressed Antialiased Video Overlays”, 1995 IEEE International Solid-State Circuits Conference, pp. 286-287.

Affiliated with

Also associated with

Rating

Error detecting circuit in a line length decoding system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Error detecting circuit in a line length decoding system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error detecting circuit in a line length decoding system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2539030