Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2004-03-23
2008-08-12
Malzahn, David H (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
07412475
ABSTRACT:
Embodiments of the invention are directed to circuits and techniques for computer processor register integrity checking employing digital roots, and hexadecimal digital roots (HDRs) in particular, to validate the results of arithmetic operations and register moves. These circuits thus provide extra confidence that register operations were correctly executed. A hexadecimal digital root is computed for the result of each register computation and compared to the results of the same computation performed on the HDRs of the operands. The hexadecimal digital root approach may be simply implemented with standard combinatoric logic. Validation is accomplished in a single clock cycle so that there is no added system delay or latency. The circuits and methods described herein have comparatively little impact on processor real estate.
REFERENCES:
B. Parhami, “A Note on Digital Filter Implementation Using Hybrid RNS-Binary Arithmetic,” Signal Processing, vol. 51, No. 1, pp. 65-67, 1996.
B. Parhami, “RNS Representations with Redundant Residues,” Proc. of the 35th Asilomar Conf. on Signals, Systems, and Computers, Pacific Grove, CA, pp. 1651-1655, Nov. 4-7, 2001.
M. J. Flynn,EE 486 Lecture 4: Residue Arithmetic, Jan. 14, 2003, available at http://www.stanford.edu/class/ee486/doc/lecture4.pdf, (last visited Jun. 2, 2004).
Chapin IP Law LLC
Malzahn David H
Sun Microsystems Inc.
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