Error detecting and correcting method and system

Details Error detecting and correcting method and system Error detecting and correcting method and system

1992-12-07

1996-10-08

Envall, Jr., Roy N.

Excavating

371 372, H03M 1300

Patent

active

055638945

ABSTRACT:
An error detecting and correcting apparatus includes a unit for receiving an encoded word including a plurality of b-bit bytes (b is an integer not less than two) and generating syndrome from the encoded word according to a first parity check matrix H.sub.1, and a unit for correcting errors in the received encoded word based on the syndrome.

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T. Rao et al.; "Error-Control Coding for Computer Systems"; 1989; pp. 230-245.
E. Fujiwara et al, "Single b-Bit Error Correcting and Double Bit Error Detecting Codes for High Speed Memory Systems"; 1992, pp. 894-500.
Fujiwara, Eiji and Taku Gohya, "A Design Method for Single Byte Error Correcting-Double Bit Error Detecting Codes," Transactions of the IEICE of Japan, vol. 91, No. 78, pp. 17-22. (Japanese).
Fujiwara, Eiji and Taku Gohya, "Single Byte Error Correcting-Double Bit Error Detecting (SbEC-DED) Codes," Proc. 1991, IEEE Int. Symp. on Inform. Theory, Jun. 1991, p. 140. (English).

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