Error detecting and correcting apparatus and method with transpa

Details Error detecting and correcting apparatus and method with transpa Error detecting and correcting apparatus and method with transpa

1992-04-24

1994-10-18

Atkinson, Charles E.

Excavating

H03M 1300

Patent

active

053575296

ABSTRACT:
System for testing memory associated with a set of check bits in an EDC system. The circuitry of the invention includes an EDC circuit; multiplexers; and a memory with first storage bits, second storage bits, and third storage bits. In writing data to the memory, a multi-bit data word having a first group of data bits and a second group of data bits is first received from a CPU bus. The first group of bits is written to the first storage bits. In a "normal" mode, the second group of bits is written to the second storage bits. A set of check bits are calculated by the EDC circuit and written to the third storage bits. In the "swap" mode, the second group of data bits is stored in the third storage bits. "Alternate" bits are calculated by the EDC circuit, and written to the second storage bits. In memory reads, contents of all of the storage bits are received from the memory and directed to the error detecting circuit. The contents of the first storage bits are directed to error correction circuit. In the normal mode, the contents of the second storage bits are directed to the error correction circuit; this data is corrected if necessary, and placed on the CPU bus. In the swap mode, the contents of the third storage bits are supplied to the error correcting circuit and, along with the contents of the first storage bits, placed on the CPU bus without error correction.

REFERENCES:
patent: 4384348 (1983-05-01), Nozaki
patent: 4604750 (1986-08-01), Manton et al.
patent: 4617664 (1986-10-01), Aichelmann, Jr. et al.
patent: 4782486 (1988-11-01), Lipcon et al.

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