Error density detector

Communications: electrical – Digital comparator systems

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Details

235 92EC, 245 92R, H03K 518

Patent

active

040805891

ABSTRACT:
An initial error indicated by a pulse at the binary input is applied through a gating circuit to trigger a monostable multivibrator (one-shot) to start a timing interval. The output of the one-shot is applied to a second gating circuit which inhibits the first gating circuit to prevent retriggering of the one-shot. Subsequent error pulses are then applied directly to a counting mechanism which counts the errors which occur during the predetermined time interval established by the one-shot. An acceptable error density is established by the predetermined time interval for the one-shot in relation to the number of errors that would occur during this predetermined time interval. If the number of errors which occur exceeds the acceptable error density, the counting circuit puts out a signal which may be applied to an alarm (or framing) circuit. Once the error counter produces an output, i.e., exceeds the acceptable error density, the counter applies a binary indication to the second gating circuit which causes the first gating circuit to retrigger the one-shot. Further, each error pulse which occurs before the one-shot times out will now trigger the one-shot. In order for the circuit to reset, an error-free period, equal to the period of the one-shot, must occur.

REFERENCES:
patent: 3036290 (1962-05-01), Zarouni
patent: 3396368 (1968-08-01), Lakhani
patent: 3525044 (1970-08-01), Richmond
patent: 3646517 (1972-02-01), Waters
patent: 3725860 (1973-04-01), Kemper et al.
Austin et al., Error Frequency Warning Detector. . ., Nov., 1969, IBM Tech. Discl. Bull., vol. 12, No. 6, p. 895.

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