Error correction system including a plurality of processor eleme

Details Error correction system including a plurality of processor eleme Error correction system including a plurality of processor eleme

1991-06-07

1994-05-24

Canney, Vincent P.

Excavating

371 381, 371 44, G06F 1100

Patent

active

053156005

ABSTRACT:
Respective processes of decoding in error correction are subjected to parallel processing using a plurality of processing elements (PEs) each having the same configuration. At any given time, when processing of one process has been terminated, processing proceeds to a PE having the highest priority among PEs waiting for processing. The PE which has received data recognizes and executes the next process for that data.

REFERENCES:
patent: 3534331 (1970-10-01), Kautz
patent: 4649541 (1987-03-01), Lahmeyer
patent: 4747103 (1988-05-01), Iwamura et al.
patent: 4751704 (1988-06-01), Kojima
patent: 4882731 (1989-11-01), Van Gils
patent: 5068857 (1991-11-01), Yoshida
patent: 5099483 (1992-03-01), Kadokawa
Clark, Jr., et al., "Error Correction Coding for Digital Communications" Plenum Press, New York, 1981, pp. 188 through 195.

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