Error correction system

Details Error correction system Error correction system

1986-08-11

1988-10-04

Smith, Jerry

Excavating

371 38, G06F 1110

Patent

active

047759798

ABSTRACT:
An error correction system for a memory device of the type in which a data of plurality of bits is stored in a storage in the form of a coded word having as an end portion thereof a plurality of check bits produced in accordance with a predetermined parity check matrix H, and a random error of at most Q bits contained in a corresponding word read from the storage is corrected on the basis of a plurality of syndrome bits produced in accordance with the predetermined parity check matrix H. A parity check matrix H' is generated by adding a unit matrix which is formed of l.times.l bits (where l>Q), to the predetermined parity check matrix H, and the check bits and the syndrome bits are produced in accordance with the parity check matrix H', to enable correction of both a block error of at most l bits and a random error to be corrected.

REFERENCES:
patent: 3638182 (1972-01-01), Burton
patent: 4214228 (1980-07-01), Nara
patent: 4592054 (1986-05-01), Namekawa
patent: 4631725 (1986-12-01), Takamura

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