Error correction system

Excavating

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G06F 1110

Patent

active

045063656

ABSTRACT:
A method and apparatus for correcting single bit errors in data stored in a first memory includes a dynamic shift register for dividing data by a polynomial during the time the data is being written into the first memory resulting in the generation of a remainder which is stored in a second memory. When reading the data from the first memory, the data is again divided by the same polynomial. The remainder generated by the second division is compared with the remainder stored in the second memory. If the remainders do not match, indicating an error was introduced into the data during storage or retrieval of the data in the first memory, the remainder stored in the second memory is shifted into the dynamic shift register and followed by the shifting of a number of zero bits into the shift register which is equal to the maximum number of bits in the data located in the second memory. As each zero bit is shifted into the shift register, a bit counter is incremented and the output bit of each stage of the shift register is examined. When the output of all the stages in the shift register except the last stage is zero and the last stage contains a binary bit one, the count of the bit counter points to the bit location in the data stored in the second memory locating the bit that is in error.

REFERENCES:
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Lewin, Theory and Design of Digital Computer Systems, 1980, p. 348.
Peterson & Weldon, Error-Correcting Codes, 2nd edition 1972, MIT Press, pp. 357-373.

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