Error correction of digital signals

Communications: electrical – Digital comparator systems

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3401461AL, 3401461AV, G06F 1112

Patent

active

040742288

ABSTRACT:
Data bits are combined at a transmitter with parity check code bits and convolutional check code bits. On reception the parity check code bits are decoded to determine the error probability in the received signal. The convolutional check code bits are used to correct the received data according to a correction algorithm which is defined in dependence on the error probability revealed by the parity check code bits. The received data is divided into bytes and each byte is given a respective error probability rating. Circuitry including logic gates and shift registers are used to carry out the encoding, decoding and correction operations.

REFERENCES:
patent: 3372376 (1968-03-01), Helm
patent: 3418630 (1968-12-01), Van Duuren
patent: 3506961 (1970-04-01), Abramson et al.
patent: 3668631 (1972-06-01), Griffith et al.
patent: 3988677 (1976-10-01), Fletcher et al.

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