Patent
1997-08-26
2000-01-25
Teska, Kevin J.
G06F 9455
Patent
active
060186267
ABSTRACT:
An error correction system (10) is provided for correcting up to two bits per sector stored in a solid state non-volatile memory (12) which emulates a disk drive. The error correction system (10) includes an ECC/remainder generator (100), a bank of remainder registers (102), and a calculation circuit (104), all under supervision of a controller (106). During a write-to-memory operation, error correction system (10) generates ECC bytes for storage in the memory (12). In a write operation, an entire sector acquired from memory (12) is used to generate ECC check remainder bytes REM.sub.0 -REM.sub.3. The check remainder bytes REM.sub.0 -REM.sub.3 are utilized to generates syndromes S.sub.1, S.sub.3 and a factor S.sub.B, the syndromes in turn being used to obtain either one or two error location positions (.alpha..sup.L1, .alpha..sup.L2). The mathematical calculation circuit (104) not only generates the syndromes S.sub.1, S.sub.3 and factor S.sub.B, as well as the error location positions (.alpha..sup.L1, .alpha..sup.L2), but also generates the addresses of the bit errors in the sector (L1-64 [complemented], L2-64 [complemented].
REFERENCES:
patent: 4642759 (1987-02-01), Foster
patent: 4718064 (1988-01-01), Edwards et al.
patent: 5062042 (1991-10-01), Binkley et al.
patent: 5077736 (1991-12-01), Dunphy, Jr. et al.
patent: 5077737 (1991-12-01), Leger et al.
patent: 5131089 (1992-07-01), Cole
patent: 5218691 (1993-06-01), Tuma et al.
patent: 5289477 (1994-02-01), Lenta et al.
patent: 5291584 (1994-03-01), Challa et al.
patent: 5297148 (1994-03-01), Harari et al.
patent: 5359726 (1994-10-01), Thomas
patent: 5379305 (1995-01-01), Weng
patent: 5404361 (1995-04-01), Casorso et al.
patent: 5418752 (1995-05-01), Harari et al.
patent: 5428630 (1995-06-01), Weng et al.
patent: 5430859 (1995-07-01), Norman et al.
patent: 5438674 (1995-08-01), Keele et al.
patent: 5459742 (1995-10-01), Cassidy et al.
patent: 5459850 (1995-10-01), Clay et al.
patent: 5473765 (1995-12-01), Gibbons et al.
patent: 5479633 (1995-12-01), Wells et al.
patent: 5555402 (1996-09-01), Tuma et al.
"Byte-Wide ECC/CRC Code and Syndrome Calculator", IBM Technical Disclosure Bulletin, vol. 29, No. 5, Oct. 1986, pp. 2143-2145.
Burnam, Jr. H. Warren
Cirrus Logic Inc.
Fiul Dan
Shifrin Dan A.
Teska Kevin J.
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