Error correction for multiple bit output chips

Details Error correction for multiple bit output chips Error correction for multiple bit output chips

1984-06-29

1986-10-14

Fleming, Michael R.

Excavating

G06F 1110

Patent

active

046176640

ABSTRACT:
An error correction code, especially suited for memory chips with multi-bit outputs, in which parity bits are calculated for each byte of the word and check bits are calculated for the word as a whole. In a 4-byte, 32-bit word, eight bits of error correction can correct up to four errors if the errors are restricted to corresponding bits in the 4 bytes.

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Fault-Tolerant Design Techniques for Semiconductor Memory Applications, IBM Journal of Research & Development, vol. 28, No. 2, Mar. 1984, pp. 177-183, F. J. Aichelmann, Jr.

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