Error-correction encoding and decoding system

Details Error-correction encoding and decoding system Error-correction encoding and decoding system

1992-05-12

1994-11-15

Baker, Stephen M.

Excavating

H03M 1300, G11B 2018

Patent

active

053655303

ABSTRACT:
The present invention provides an error-correction code encoding and decoding technique in which an information amount is variable in a block, and error-correction encoding in the block can be done efficiently without a substantial change in circuit configuration regardless of information amount. An encoder comprises a C1 encoding section for encoding an Ip information series, a C3 encoding section for encoding an Is information series, a control circuit for controlling the encoding sections based on an identification signal indicating whether the Is information series is contained, and a buffer memory. If an Is information series is contained, an area corresponding to the Is information series is deleted from check symbols of the Ip information series and replaced with coded data of the Is information series. A decoder decodes a received word thus encoded. This obviates superimposition-separation of C3 information, thereby realizing efficient error-correction encoding in a block, while maintaining an information amount of a block variable, without any change in circuit configuration based on information amount.

REFERENCES:
Kasahara, M. et al., "New Classes of Binary Codes Constructed on the Basis of Concaterated Codes and Product Codes", IEEE Trans. on Information Theory, vol. IT-22, No. 4, Jul. 1976, pp. 462-468.
1990 International Symposium . . . "The Superimposed Codes and its Application to Digital VCR" Inoue, Yoshida & Ishida.
IEEE Transactions on Consumer Electronics, vol. 37, No. 3, 8-91 "An Experimental Home-Use Digital VCR W/3-Dimensional DCT . . . ".

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