Error correction decoder that operates in either ARDS system or

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371 41, 375340, H23M 1300

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active

057455031

ABSTRACT:
A decoding method and circuit takes into consideration two different techniques of using offset words in error correction coding by subtracting the offset word in a parallel mode from a calculated syndrome. In an error correction decoder (36) an entire incoming data block (26 bits, where 16 are data and 10 are parity) is read into a polynomial divider (11). The invention enables a single data receiver (30) to operate using error correction offset, words A, B, C, and D, in a first radio data system, or the offset words A, B, C, D, and E, in a second radio data system. In accordance with an error correction decoder of this invention the decoder is arranged with a parallel-bit output offset counter (13), an offset word generator (16), and a syndrome storage register (15) coupled to the polynomial divider (11) for enabling the subtracting of an offset word, in parallel, from calculated syndromes.

REFERENCES:
patent: 5157669 (1992-10-01), Yu et al.
patent: 5173925 (1992-12-01), Mizoguchi
patent: 5325372 (1994-06-01), Ish-Shalom
patent: 5396653 (1995-03-01), Kivari et al.
patent: 5430740 (1995-07-01), Kivari et al.
Specification of the Radio Data System, published in Apr. 1992 by the European Telecommunications Standardization Institute (ETSI), Section B.2.2.

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