Error correction code pipeline for interleaved memory system

Details Error correction code pipeline for interleaved memory system Error correction code pipeline for interleaved memory system

1993-05-07

1994-08-02

Beausoliel, Jr., Robert W.

Excavating

371 402, 371 375, H03M 1300

Patent

active

053352343

ABSTRACT:
A data stream process pipeline and method of transferring data from a storage device to a central processor unit (CPU) or cache memory includes an input latch arrangement, error correcting circuitry, and an output latch arrangement. In embodiments of the present invention the input and output latch arrangements include two latches and means for multiplexing the outputs of the two latches.

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