Error correction code on add-on cards for writing portions of da

Details Error correction code on add-on cards for writing portions of da Error correction code on add-on cards for writing portions of da

1993-11-17

1995-09-19

Harrell, Robert B.

Excavating

371 402, 364DIG1, 364DIG2, 364243, 364265, 3642653, 3642663, 3649439, 3649449, 3649456, 395432, 395442, 395482, 395494, G06F 1110

Patent

active

054524296

ABSTRACT:
The present invention provides a computer system and method of using the same. Add-on memory cards for the system are provided which cards have error correction code logic on the card, and logic to do partial writes of data words. The system has a central processing unit (CPU), a BUS interconnecting the CPU and the add-on memory cards. The CPU or associated components are configured to write data and read data from the add-on memory as several data bytes constituting data words. The system is further configured either within the CPU or as a separate function to generate parity bits associated with each of the bytes of data the CPU writes to the add-on memory and to read parity bits associated with data the CPU reads from the add-on memory and regenerate new parity bits and compare the newly generated parity bits with the original parity bits to detect data errors on data read from the add-on memory. The system itself does not contain error correction code (ECC). The add-on memory has ECC logic to identify any byte having a single bit error in the data bytes or the parity bits written by the CPU to the add-on memory and to correct all single bit errors in data read from the add-on memory to the CPU. The error correcting code includes logic to generate parity bits in the data bytes written by the CPU to the add-on memory and logic to compare the parity bits written by the CPU with those generated by the error correcting code logic.

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